Creating Single-Ended or Differential IO Ports - 2025.2 English - UG899

ug899IO Planning for Zynq UltraScale+ MPSoCs‌ - 2025.2 English - UG899 Vivado Desn Suite User Guide: IO and Clock Planning (UG899) Document ID UG899 Release DateIO Planning for UltraScale Architecture Memory IP - 2025.2 English - UG899 Vivado Desn Suite User Guide: IO and Clock Planning (UG899) Document ID UG899